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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7540 Group is the 8-bit microcomputer based on the 740 family core technology. The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an A-D converter, and is useful for control of home electric appliances and office automation equipment.
* *
FEATURES
* * * * * * * * * *
Basic machine-language instructions ....................................... 71 The minimum instruction execution time .......................... 0.50 s (at 8 MHz oscillation frequency for the shortest instruction) Memory size ROM ............................................ 16K to 32K bytes RAM .............................................. 512 to 768 bytes Programmable I/O ports ........................................................... 29 (25 in 32-pin version) Interrupts .................................................. 15 sources, 15 vectors (14 sources, 14 vectors for 32-pin version) Timers ............................................................................ 8-bit ! 4 16-bit ! 1 Serial I/O1 ...................................................................... 8-bit ! 1 (UART or Clock-synchronized) Serial I/O2 ...................................................................... 8-bit ! 1 (Clock-synchronized) A-D converter ................................................ 10-bit ! 8 channels (6 channels for 32-pin version) Clock generating circuit ............................................. Built-in type
* *
(low-power dissipation by a ring oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation) Watchdog timer ............................................................ 16-bit ! 1 Power source voltage XIN oscillation frequency at ceramic oscillation, in high-speed mode At 8 MHz .................................................................... 4.0 to 5.5 V At 4 MHz .................................................................... 2.4 to 5.5 V At 2 MHz .................................................................... 2.2 to 5.5 V XIN oscillation frequency at RC oscillation At 4 MHz .................................................................... 4.0 to 5.5 V At 2 MHz .................................................................... 2.4 to 5.5 V At 1 MHz .................................................................... 2.2 to 5.5 V Power dissipation ............................................ 25 mW (standard) Operating temperature range ................................... -20 to 85 C (-40 to 85 C for extended operating temperature version)
APPLICATION
Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc. Note: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected as the synchronized clock.
23
20
24
22
19
18
P07 P10/RXD1 P11/TXD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1
21
17
P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0
PIN CONFIGURATION (TOP VIEW)
25 26 27 28 29 30 31 32
16 15 14
M37540M4-XXXGP M37540E8GP
13 12 11 10 9
P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN
3
4
Package type: 32P6B-A
Fig. 1 M37540M4-XXXGP, M37540E8GP pin configuration
P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC
1
2
5
6
7
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
Package type: 36P2R-A
Fig. 2 M37540M4-XXXFP, M37540E8FP pin configuration
M37540M4-XXXFP M37540E8FP
P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC XIN XOUT VSS
1 2 3 4 5
32 31 30 29 28
P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0)
M37540M4-XXXSP M37540E8SP
6 7 8 9 10 11 12 13 14 15 16
27 26 25 24 23 22 21 20 19 18 17
Package type: 32P4B
Fig. 3 M37540M4-XXXSP, M37540E8SP pin configuration
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FUNCTIONAL BLOCK DIAGRAM (Package: 32P6B)
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Clock input Clock output Reset input VSS VCC CNVSS
7 8 6 11
X IN X OUT RESET
L
FUNCTIONAL BLOCK
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Clock generating circuit
CPU
RAM ROM
X Prescaler X (8)
CNTR0
A
Prescaler 1 (8)
Timer 1 (8) Timer X (8)
TXOUT
5 4 3 2 1 32 31
17 16 15 14 13 12
30 29 28 27 26
25 24 23 22 21 20 19 18
VREF
MITSUBISHI MICROCOMPUTERS
7540 Group
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wakeup
Fig. 4 Functional block diagram (32P6B package)
Y Prescaler Y (8) S PC H PS PCL Prescaler Z (8) Timer Y (8)
TYOUT
Timer Z (8)
TZOUT
Watchdog timer
INT0
Reset
Timer A (16)
CNTR1
0
A-D converter (10) SI/O1(8) SI/O2(8)
INT0
P3(6) P2(6)
P1(5)
P0(8)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3
12
26 25 24 23 22 21 20 19
11 10 9 8 7 6 5 4
3 2 1 36 35
34 33 32 31 30 29 28 27
VREF
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wakeup
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FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
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Clock input Clock output X IN X OUT VSS VCC
15 13 14
Reset input RESET CNVSS
L
16
17
18
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Clock generating circuit
CPU
RAM ROM
X
CNTR0
A Prescaler X (8) Prescaler Y (8) S PCH PS PCL Prescaler Z (8)
Prescaler 1 (8)
Timer 1 (8) Timer X (8)
TXOUT
Fig. 5 Functional block diagram (36P2R package)
Y Timer Y (8)
TYOUT
Timer Z (8)
TZOUT
Watchdog timer
INT0
Reset
Timer A (16)
CNTR1
0
A-D converter (10) SI/O1(8) SI/O2(8)
INT0 INT1
P3(8)
P2(8)
P1(5)
P0(8)
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
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Clock input Clock output X IN X OUT VSS VCC CNVSS
12 13 11 16
Reset input RESET
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Clock generating circuit Prescaler 1 (8)
CPU Timer 1 (8) Timer X (8)
TXOUT
RAM
A X
CNTR0
ROM
Prescaler X (8) Prescaler Y (8) Prescaler Z (8) Timer A (16)
CNTR1 INT0
10
22 21 20 19 18 17
987654
3 2 1 32 31
30 29 28 27 26 25 24 23
VREF
MITSUBISHI MICROCOMPUTERS
7540 Group
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wakeup
Fig. 6 Functional block diagram (32P4B package)
Y S PCH PS PCL Timer Y (8)
TYOUT
Timer Z (8)
TZOUT
Watchdog timer
Reset
0
A-D converter (10) SI/O1(8) SI/O2(8)
INT0
P3(6) P2(6)
P1(5)
P0(8)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description Pin Vcc, Vss VREF CNVss RESET XIN XOUT Name Power source Analog reference voltage CNVss Reset input Clock input Clock output *Reference voltage input pin for A-D converter *Chip operating mode control pin, which is always connected to Vss. *Reset input pin for active "L" *Input and output pins for main clock generating circuit *Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins. *For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. P00/CNTR1 P01/TYOUT P02/TZOUT P03/TXOUT P04-P07 I/O port P0 *8-bit I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *Whether a built-in pull-up resistor is to be used or not can be determined by program. P10/RxD1 P11/TxD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0- P27/AN7 I/O port P2 I/O port P1 *5-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *CMOS/TTL level can be switched for P10, P12 and P13 *8-bit I/O port having almost the same function as P0 *CMOS compatible input level *CMOS 3-state output structure P30-P35 I/O port P3 *8-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37). *CMOS 3-state output structure *P30 to P36 can output a large current for driving LED. P36/INT1 P37/INT0 *Whether a built-in pull-up resistor is to be used or not can be determined by program. *Interrupt input pins *Input pins for A-D converter *Serial I/O1 function pin *Serial I/O1 function pin *Serial I/O2 function pin *Timer X function pin * Key-input (key-on wake up interrupt input) pins * Timer Y, timer Z, timer X and timer A function pin Function *Apply voltage of 2.2-5.5 V to Vcc, and 0 V to Vss. Function expect a port function
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 7540 group as follow: Memory type Support for Mask ROM version, One Time PROM version, and Emulator MCU .
Memory size ROM/PROM size ................................................ 16 K to 32 K bytes RAM size ................................................................ 512 to 768 bytes Package 32P4B ........................................... 32-pin shrink plastic molded DIP 32P6B-A ...................................... 0.8 mm-pitch plastic molded QFP 36P2R-A ..................................... 0.8 mm-pitch plastic molded SOP 42S1M ..................................... 42-pin shrink ceramic PIGGY BACK
ROM size (bytes)
Under development
M37540E8
32K
Under development
M37540M4T
16K
M37540M4
Under development
0
384
512
768
RAM size (bytes)
Note: Products under development***the development schedule and specification may be revised without notice.
Fig. 7 Memory expansion plan Currently supported products are listed below. Table 2 List of supported products Product M37540M4-XXXSP M37540M4-XXXFP M37540M4T-XXXFP M37540M4-XXXGP M37540M4T-XXXGP M37540E8SP M37540E8FP M37540E8GP M37540RSS 768 32768 (32638) 768 16384 (16254) 512 (P) ROM size (bytes) RAM size Package ROM size for User () (bytes) 32P4B 36P2R-A 32P6B-A 32P4B Mask ROM version Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version Mask ROM version (extended operating temperature version) One Time PROM version (blank) Remarks
36P2R-A One Time PROM version (blank) 32P6B-A One Time PROM version (blank) 42S1M Emulator MCU
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
b7 b0
CPU mode register (CPUM: address 003B 16) Processor mode bits (Note 1) b1 b0 0 0 Single-chip mode 01 10 Not available 11 Stack page selection bit 0 : 0 page 1 : 1 page Ring oscillator oscillation control bit 0 : Ring oscillator oscillation enabled 1 : Ring oscillator oscillation stop XIN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation Clock division ratio selection bits b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f() = f(XIN) (Double-speed mode)(Note 2)
Central Processing Unit (CPU)
The 7540 Group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the 740 Family Software MANUAL for details on each instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions cannot be used. 2. The MUL and DIV instructions can be used. 3. The WIT instruction can be used. 4. The STP instruction can be used. (This instruction cannot be used while CPU operates by a ring oscillator.) [CPU mode register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method.
Note 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU "M37540RSS".) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected.
Fig. 8 Structure of CPU mode register
After releasing reset
Start with a built-in ring oscillator
Switch the oscillation mode selection bit (bit 5 of CPUM)
An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts.
Wait by ring oscillator operation until establishment of oscillator clock
When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from a ring oscillator meets the requirement).
Switch the clock division ratio selection bits (bits 6 and 7 of CPUM)
Switch to other mode except a ring oscillator. At the same time, select the double-speed, high-speed, or middle-speed mode.
Main routine
Fig. 9 Switching method of CPU mode register
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Memory
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors.
Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
000016 SFR area 004016 010016 Zero page
RAM RAM area
RAM capacity (bytes) address XXXX16
XXXX16 Reserved area 044016 Not used YYYY16 Reserved ROM area
(128 bytes)
512 768
023F16 033F16
ZZZZ16
ROM ROM area
ROM capacity (bytes) address YYYY16 address ZZZZ16
FF0016
16384 32768
C00016 800016
C08016 808016
FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area
Special page
Fig. 10 Memory map diagram
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516
Timer Y, Z mode register (TYZM) Prescaler Y (PREY) Timer Y secondary (TYS) Timer Y primary (TYP) Timer Y, Z waveform output control register (PUM) Prescaler Z (PREZ) Timer Z secondary (TZS) Timer Z primary (TZP) Prescaler 1 (PRE1) Timer 1 (T1) One-shot start register (ONS) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS)
Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2)
A-D control register (ADCON) A-D conversion register (low-order) (ADL) A-D conversion register (high-order) (ADH)
Pull-up control register (PULL) Port P1P3 control register (P1P3C) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Timer A mode register (TAM) Timer A (low-order) (TAL) Timer A (high-order) (TAH)
003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Note : Do not access to the SFR area including nothing.
Fig. 11 Memory map of special function register (SFR)
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I/O Ports
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Direction registers] PiD The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When "1" is set to the bit corresponding to a pin, this pin becomes an output port. When "0" is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating.
[Pull-up control register] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. [Port P1P3 control register] P1P3C By setting the port P1P3 control register (address 001716), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P36, and P37 by program.
b7
b0
Pull-up control register (PULL: address 0016 16, initial value: 00 16)
P00 pull-up control bit P01 pull-up control bit P02, P03 pull-up control bit P04 - P07 pull-up control bit P30 - P33 pull-up control bit P34 pull-up control bit P35, P36 pull-up control bit P37 pull-up control bit
0 : Pull-up Off 1 : Pull-up On
Note 1: Pins set to output ports are disconnected from pull-up control. 2: Set the P35, P36 pull-up control bit to "1" (initial value: "0") for 32-pin version.
Fig. 12 Structure of pull-up control register
b7
b0
Port P1P3 control register (P1P3C: address 0017 16, initial value: 00 16) P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit 0 : CMOS level 1 : TTL level P10,P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used
Note: Keep setting the P3 6/INT1 input level selection bit to "0" (initial value) for 32-pin version.
Fig. 13 Structure of port P1P3 control register
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 3 I/O port function table Pin P00/CNTR1 P01/TYOUT P02/TZOUT P03/TXOUT P04-P07 Name Input/output I/O format *CMOS compatible input level *CMOS 3-state output (Note) Non-port function Key input interrupt Related SFRs Pull-up control register Timer Y mode register Timer Z mode register Timer X mode register Timer Y,Z waveform output control register Timer A mode register Serial I/O1 control register Serial I/O1 control register Serial I/O2 control register Timer X mode register A-D control register Diagram No. (1) (2) (3) (4) I/O port P0 I/O individual bits
P10/RxD1 P11/TxD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0
I/O port P1
Serial I/O1 function input/output Serial I/O2 function input/output Timer X function input/output A-D conversion input
(5) (6) (7) (8) (9) (10) (11)
P20/AN0-P27/AN7 I/O port P2 P30-P35 P36/INT1 P37/INT0 Note: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level. I/O port P3
External interrupt input
Interrupt edge selection register
(12)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1)Port P00
Pull-up control Direction register
(2)Ports P01, P02
Pull-up control Direction register
Data bus
Port latch
Data bus
Port latch
CNTR1 interrupt input To key input interrupt generating circuit
Pulse output mode Timer output To key input interrupt generating circuit
(3)Port P03
Pull-up control Direction register
(4)Ports P04-P07
Pull-up control Direction register
Data bus
Port latch Timer output P03/TXOUT output valid
Data bus
Port latch
To key input interrupt generating circuit To key input interrupt generating circuit
(5)Port P10
Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch P10, P12, P13 input level selection bit
(6)Port P11
P11/TxD1 P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register
Data bus
Port latch
Serial I/O1 input
*
Serial I/O1 output
(7)Port P12
Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit SCLK2 pin selection bit
Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus
Port latch
P10, P12, P13 input level selection bit Serial I/O1, serial I/O2 clock output Serial I/O1, serial I/O2 clock input
* *
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
Fig. 14 Block diagram of ports (1)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(8) Port P13
(9) Port P14
SDATA2 output in operation signal SDATA2 pin selection bit Serial I/O mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Direction register
Port latch
Data bus
Port latch Pulse output mode Timer output CNTR0 interrupt input
P10, P12, P13 input level selection bit Serial I/O1 ready output Serial I/O2 output Serial I/O2 input
*
(10) Ports P20-P27
Direction register
(11) Ports P30-P35
Pull-up control Direction register
Data bus
Port latch Data bus Port latch
A-D converter input Analog input pin selection bit
(12) Ports P36, P37
Pull-up control Direction register
Data bus
Port latch
P3 input level selection bit
INT interrupt input
* *
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
Fig. 15 Block diagram of ports (2)
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Interrupts
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts occur by 15 different sources : 5 external sources, 9 internal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority.
Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. Notes on use When the active edge of an external interrupt (INT0, INT1,CNTR0) is set, the interrupt request bit may be set. Therefore, please take following sequence: 1. Disable the external interrupt which is selected. 2. Change the active edge in interrupt edge selection register. (in case of CNTR0: Timer X mode register, in case of CNTR1: Timer A mode register) 3. Clear the set interrupt request bit to "0". 4. Enable the external interrupt which is selected.
Table 4 Interrupt vector address and priority Vector addresses (Note 1) Interrupt source Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit Priority 1 2 3
High-order Low-order
Interrupt request generating conditions At reset input At completion of serial I/O1 data receive
Remarks Non-maskable Valid only when serial I/O1 is selected
FFFD16 FFFB16 FFF916
FFFC16 FFFA16 FFF816
At completion of serial I/O1 transmit shift or Valid only when serial I/O1 is selected when transmit buffer is empty At detection of either rising or falling edge of External interrupt INT0 input (active edge selectable) At detection of either rising or falling edge of External interrupt INT1 input (active edge selectable) At falling of conjunction of input logical level for External interrupt (valid at falling) port P0 (at input) At detection of either rising or falling edge of External interrupt (active edge selectable) CNTR0 input At detection of either rising or falling edge of External interrupt CNTR1 input (active edge selectable) At timer X underflow At timer Y underflow At timer Z underflow At timer A underflow At completion of transmit/receive shift At completion of A-D conversion At timer 1 underflow Not available Non-maskable software interrupt STP release timer underflow
INT0
4
FFF716
FFF616
INT1 (Note 3)
5
FFF516
FFF416
Key-on wake-up
6
FFF316
FFF216
CNTR0
7
FFF116
FFF016
CNTR1
8
FFEF16
FFEE16
Timer X Timer Y Timer Z Timer A Serial I/O2 A-D conversion Timer 1 Reserved area BRK instruction
9 10 11 12 13 14 15 16
FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16
FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16
FFDD16 FFDC16 At BRK instruction execution 17 Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: It is an interrupt which can use only for 36 pin version.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag I
BRK instruction Reset
Fig. 16 Interrupt control
b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns "0" when read) P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit Timer X interrupt request bit
Interrupt request
0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer Y interrupt request bit Timer Z interrupt request bit Timer A interrupt request bit Serial I/O2 interrupt request bit A-D conversion interrupt request bit Timer 1 interrupt request bit Not used (returns "0" when read)
0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt control register 1 (ICON1 : address 003E16) Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer X interrupt enable bit
0 : Interrupts disabled 1 : Interrupts enabled
b7
b0 Interrupt control register 2 (ICON2 : address 003F16) Timer Y interrupt enable bit Timer Z interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit A-D conversion interrupt enable bit Timer 1 interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit)
0 : Interrupts disabled 1 : Interrupts enabled
Fig. 17 Structure of Interrupt-related registers
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying "L" level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports.
Port PXx "L" level output PULL register bit 3 = "0" * P07 output ** Port P07 latch
Falling edge detection
Port P07 Direction register = "1" Key input interrupt request
PULL register bit 3 = "0" * P06 output ** Port P06 latch
Port P06 Direction register = "1"
Falling edge detection
PULL register bit 3 = "0" * P05 output ** Port P05 latch
Port P05 Direction register = "1"
Falling edge detection
PULL register bit 3 = "0" * P04 output ** Port P04 latch
Port P04 Direction register = "1"
Falling edge detection
PULL register bit 2 = "1" * P03 input ** Port P03 latch
Port P03 Direction register = "0"
Falling edge detection
Port P0 Input read circuit
PULL register bit 2 = "1" * P02 input ** Port P02 latch
Port P02 Direction register = "0"
Falling edge detection
PULL register bit 1 = "1" * P01 input ** Port P01 latch
Port P01 Direction register = "0"
Falling edge detection
PULL register bit 0 = "1" * P00 input ** Port P00 latch
Port P00 Direction register = "0"
Falling edge detection
* P-channel transistor for pull-up ** CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P0 block diagram
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timers
The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y and timer Z. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches "0", an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to "1".
b7
b0 Timer A mode register (TAM : address 001D16) Not used (return "0" when read) Timer A operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR1 interrupt Timer A stop control bit 0 : Count start 1 : Count stop
qTimer 1
Prescaler 1 always counts f(XIN)/16. Timer 1 always counts the prescaler 1 output and periodically sets the interrupt request bit.
qTimer A
Timer A is a 16-bit timer that can be selected in one of four modes. * Timer Mode The timer counts f(XIN)/16. * Period Measurement Mode CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer A latch is reloaded in timer A and timer A continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer A is read once after the reload. The rising/falling timing of CNTR1 pin input signal is found by CNTR1 interrupt. * Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. * Pulse Width HL Continuously Measure-ment Mode CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. s Note q CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit.
Fig. 19 Structure of timer A mode register
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qTimer X
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X can be selected in one of 4 operating modes by setting the timer X mode register. * Timer Mode The timer counts the signal selected by the timer X count source selection bits. * Pulse Output Mode The timer counts the signal selected by the timer X count source selection bits, and outputs a signal whose polarity is inverted each time the timer value reaches "0", from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the output of the CNTR0 pin is started with an "H" output. At "1", this output is started with an "L" output. When using a timer in this mode, set the port P14 direction register to output mode. Also, in the pulse output mode, the inverted waveform of pulse output from CNTR0 pin can be output from TXOUT pin by setting the P03/TXOUT output valid bit to "1" . When using a timer in this mode, set the port P03 direction register to output mode. * Event Counter Mode The operation in the event counter mode is the same as that in the timer mode except that the timer counts the input signal from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the timer counts the rising edge of the CNTR0 pin. When this bit is "1", the timer counts the falling edge of the CNTR0 pin. * Pulse Width Measurement Mode When the CNTR0 active edge switch bit is "0", the timer counts the signal selected by the timer X count source selection bit while the CNTR0 pin is "H". When this bit is "1", the timer counts the signal while the CNTR0 pin is "L". In any mode, the timer count can be stopped by setting the timer X count stop bit to "1". Each time the timer overflows, the interrupt request bit is set.
b7
b0
Timer X mode register (TXM : address 002B16) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop P03/TXOUT output valid bit 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR 0 output) Not used (return "0" when read)
Fig. 20 Structure of timer X mode register
b7
b0
Timer count source set register (TCSS : address 002E 16) Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) 1 1 : Not available Timer Y count source selection bits b3 b2 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : Ring oscillator output (Note) 1 1 : Not available Timer Z count source selection bits b5 b4 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : Timer Y underflow 1 1 : Not available Fix this bit to "0". Not used (return "0" when read) Note : System operates using a ring oscillator as a count source by setting the ring oscillator to oscillation enabled by bit 3 of CPUM.
Fig. 21 Timer count source set register
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qTimer Y
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y is an 8-bit timer and can be selected in one of 2 operating modes by setting the timer Y, Z mode register (TYZM). * Timer mode * Programmable waveform generation mode The division ratio of timer Y and prescaler Y is 1/(n+1) provided that the value of the timer latch or prescaler Y latch is n. (1)Timer mode * Mode select Timer mode is selected by setting timer Y operation mode bit (b0) of TYZM to "0". * Count source select The count source is f(XIN)/2 or f(XIN)/16. * Interrupt When an underflow occurs, timer Y interrupt request bit (b0) of IREQ2 is set to "1". * Operation description After reset release, timer Y is operating because the timer Y count stop bit (b3) of TYZM is "0". Timer operation is stopped by setting b3 of TYZM to "1". In the timer mode, the timer count value is set by timer Y primary latch (TYP). When a value is set to TYP while timer is stopped, the setting value is written to latch and timer simultaneously. When timer Y reaches "00", an underflow occurs at the next count pulse, and the timer Y latch is reloaded into the timer and count continues. When timer value is changed during the count operation, either "writing to latch and timer simultaneously" or "writing to only latch" can be selected by setting the timer Y write control bit (b2) of TYZM. When selecting "writing to only latch", the timer count value is changed after the next underflow. (2)Programmable waveform generation mode * Mode select Timer mode is selected by setting timer Y operation mode bit (b0) of TYZM to "1". When this mode is selected, set timer Y write control bit (b2) of TYZM to "1" ("writing to only latch" selected). * Count source select The count source is f(XIN)/2 or f(XIN)/16. * Interrupt When an underflow occurs, timer Y interrupt request bit (b0) of IREQ is set to "1".
* Operation description After reset release, timer Y is operating because the timer Y count stop bit (b3) of TYZM is "0". MCU operates in the programmable waveform generation mode when timer Y operation mode bit (b0) of TYZM is set to "1" and b3 to "0" after timer Y operation is stopped by setting b3 of TYZM to "1". In the programmable waveform generation mode, timer counts the setting value of timer Y primary latch (TYP) and the setting value of timer Y secondary latch (TYS) alternately, the waveform inverted each time TYP and TYS underflow is output from TYOUT pin. The active edge of output waveform is set by the timer Y output level latch (b4) of the timer Y, Z waveform output control register (PUM). When "0" is set to b4 of PUM, the initial state of timer at stop is "L", and "H" interval by the setting value of TYP or "L" interval by the setting value of TYS is output alternately. When "1" is set to b4 of PUM, the initial state of timer at stop is "H", and "L" interval by the setting value of TYP or "H" interval by the setting value of TYS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Y primary waveform extension control bit (b0) and the timer Y secondary waveform extension control bit (b1) of PUM to "1". As a result, the waveforms of more accurate resolution can be output. When b0 and b1 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FTYOUT = (2 ! TMCL)/(2 ! (TYP+1) + 2 ! (TYS) + (EXPYP + EXPYS)) Duty: DTYOUT = (2 ! (TYP + 1)) + EXPYP)/(2 ! (TYS + 1) + EXPYS)) TMCL: Timer Y count clock f(XIN)/2 or f(XIN)/16 TYP: Timer Y primary latch (8 bits) TYS: Timer Y secondary latch (8 bits) EXPYP: Timer Y primary waveform extension control bit (1 bit) EXPYS: Timer Y secondary waveform extension control bit (1 bit) When using the programmable waveform generation mode, note the following; Notes on using the programmable waveform generation mode * When setting and changing TYP, TYS, EXPYP and EXPYS, write to TYP at last because the setting to them is executed all at once by writing to TYP. Even when TYP is not changed, write the same value. The value is reloaded to timer at the beginning of the next primary interval. * Set by software in order not to execute the writing to timer Y primary and the timing of timer underflow simultaneously. When reading the timer Y secondary, the undefined value is read out. However, while timer counts the setting value of the timer Y secondary, the count values at the secondary interval can be identified by reading the timer Y primary. * In this mode, set port P01 which is also used as TYOUT pin to output. * B0 and b1 of PUM can be used only when "0016" is set to prescaler Y.
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qTimer Z
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Z is an 8-bit timer and can be selected in one of 4 operating modes by setting the timer YZ mode register (TYZM). * Timer mode * Programmable waveform generation mode * Programmable one-shot generation mode * Programmable wait one-shot generation mode The division ratio of timer Z and prescaler Z is 1/(n+1) provided that the value of the timer Z latch or prescaler Z latch is n. (1)Timer mode * Mode select Timer mode is selected by setting timer Z operation mode bits (b5,b4) of TYZM to "00". * Count source select The count source is f(XIN)/2, f(XIN)/16 or timer Y underflow. * Interrupt When an underflow occurs, timer Z interrupt request bit (b1) of IREQ2 is set to "1". * Operation description After reset release, timer Z is operating because the timer Z count stop bit (b7) is "0". Timer operation is stopped by setting b7 of TYZM to "1". In the timer mode, the timer count value is set by timer Z primary latch (TZP). When a value is set to TZP while timer is stopped, the setting value is written to latch and timer simultaneously. When timer Z reaches "00", an underflow occurs at the next count pulse, and the timer Z latch is reloaded into the timer and count continues. When timer value is changed during the count operation, either "writing to latch and timer simultaneously" or "writing to only latch" can be selected by setting the timer Z write control bit (b6) of TYZM. When selecting "writing to only latch", the timer count value is changed after the next underflow. (2)Programmable waveform generation mode * Mode select Timer mode is selected by setting timer Z operation mode bits (b5,b4) of TYZM to "01". When this mode is selected, set timer Z write control bit (b6) of TYZM to "1" ("writing to only latch" selected). * Count source select The count source is f(XIN)/2, f(XIN)/16 or timer Y underflow. * Interrupt When an underflow occurs, timer Z interrupt request bit (b1) of IREQ is set to "1". * Operation description After reset release, timer Z is operating because the timer Z count stop bit (b7) of TYZM is "0". MCU operates in the programmable waveform generation mode when timer Z operation mode bits (b5, b4) of TYZM is set to "01" and b7 to "0" after timer Z operation is stopped by setting b7 of TYZM to "1".
In the programmable waveform generation mode, timer counts the setting value of timer Z primary latch (TZP) and the setting value of timer Z secondary latch (TZS) alternately, the waveform inverted each time TZP and TZS underflow is output from TZOUT pin. The active edge of output waveform is set by the timer Z output level latch (b5) of the timer Y, Z waveform output control register (PUM). When "0" is set to b5 of PUM, the initial state of timer at stop is "L", and "H" interval by the setting value of TZP or "L" interval by the setting value of TZS is output alternately. When "1" is set to b5 of PUM, the initial state of timer at stop is "H", and "L" interval by the setting value of TZP or "H" interval by the setting value of TZS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (b2) and the timer Z secondary waveform extension control bit (b3) of PUM to "1". As a result, the waveforms of more accurate resolution can be output. When b2 and b3 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FTZOUT = (2 ! TMCL)/(2 ! (TZP + 1)+2 ! (TZS) + (EXPZP + EXPZS)) Duty: DTZOUT = (2 ! (TZP + 1)) + EXPZP)/(2 ! (TZS+1) + EXPZS)) TMCL: Timer Z count clock f(XIN)/2 or f(XIN)/16 TZP: Timer Z primary latch (8 bits) TZS: Timer Z secondary latch (8 bits) EXPZP: Timer Z primary waveform extension control bit (1 bit) EXPZS: Timer Z secondary waveform extension control bit (1 bit) When using the programmable waveform generation mode, note the following; Notes on using the programmable waveform generation mode * When setting and changing TZP, TZS, EXPZP and EXPZS, write to TZP at last because the setting to them is executed all at once by writing to TZP. Even when TZP is not changed, write the same value. The value is reloaded to timer at the beginning of the next primary interval. * Set by software in order not to execute the writing to timer Z primary and the timing of timer underflow simultaneously. When reading the timer Z secondary, the undefined value is read out. However, while timer counts the setting value of the timer Z secondary, the count values at the secondary interval can be identified by reading the timer Z primary. * In this mode, set port P02 which is also used as TZOUT pin to output. * B2 and b3 of PUM can be used only when "0016" is set to prescaler Z and f(XIN)/2 or f(XIN)/16 is selected as the timer Z count source.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(3)Programmable one-shot generation mode * Mode select Timer mode is selected by setting timer Z operation mode bits (b5,b4) of TYZM to "10". When this mode is selected, set timer Z write control bit (b6) of TYZM to "1" ("writing to only latch" selected). * Count source select The count source is f(XIN)/2, f(XIN)/16 or timer Y underflow. * Interrupt When an underflow occurs, timer Z interrupt request bit (b1) of IREQ2 is set to "1". * Operation description After reset release, timer Z is operating because the timer Z count stop bit (b7) of TYZM is "0". MCU operates in the programmable one-shot generation mode when timer Z operation mode bits (b5, b4) of TYZM is set to "10" after timer Z operation is stopped by setting b7 of TYZM to "1". Timer Z is enabled to accept the one-shot start trigger when "0" is written to b7 of TYZM after the timer count value is set to the timer Z primary latch (TZP). In this state, when "1" is written to the timer Z one-shot start bit (b0) of the one-shot start register (ONS), timer Z starts count operation, at the same time, the output of TZOUT pin is inverted. Timer Z counts down the value of TZP and stops after the output of TZOUT pin is inverted to the same level as the initial state when an underflow occurs. In this time, the next one-shot pulse can be output by writing b0 of ONS to "1" because this bit is initialized to "0". The active edge of the output waveform from TZOUT pin is set by the timer Z output level latch (b5) of PUM. When "0" is set to b5 of PUM, the initial level of timer at stop is "L" and "H" is output at the same time when timer starts. "H" is output in the count interval of TZP, and the output is inverted to "L" and stopped when an underflow occurs. Also, when "1" is set to b5 of PUM, the initial level of timer at stop is "H" and "L" is output at the same time when timer starts. "L" is output in the count interval of TZP, and the output is inverted to "H" and stopped when an underflow occurs. When the INT0 pin one-shot trigger control bit (b6) of PUM is set to "1", the one-shot pulse can be output by using the input of INT0 pin as a trigger. The active edge of the pulse input to INT0 pin as the trigger can be selected by the INT0 pin one-shot trigger active edge selection bit (b7) of PUM. The trigger is accepted and the one-shot pulse is generated by the falling edge of INT0 pin input when "0" is set to b7 of PUM or the rising edge of INT0 pin input when "1" is set to the b7 of PUM. Also, the INT0 interrupt occurs when the trigger is input from the INT0 pin by setting the INT0 interrupt edge selection bit (b0) of the interrupt edge selection register (INTEDGE) and the INT0 interrupt enable bit (b2) of the interrupt control register 1 (ICON1). Even when the trigger by the INT0 pin input is selected, the one-shot pulse can be output by writing to b0 of ONS. Also, in this mode, the waveform output interval of the one-shot pulse can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (b2) to "1". As a result, the waveforms of more accurate resolution can be output.
When using the programmable one-shot generation mode, note the following; Notes on using the programmable one-shot generation mode * When setting and changing TZP and EXPZS, write to TZP at last because the setting to them is executed all at once by writing to TZP. Even when TZP is not changed, write the same value. The value is reloaded to timer at the beginning of the next primary interval. * Set by software in order not to execute the writing to timer Z primary and the timing of timer underflow simultaneously. When reading the timer Z secondary, the undefined value is read out. However, while timer counts the setting value of the timer Z secondary, the count values at the secondary interval can be identified by reading the timer Z primary. * In this mode, set port P02 which is also used as TZOUT pin to output. * B2 of PUM can be used only when "0016" is set to prescaler Z and f(XIN)/2 or f(XIN)/16 is selected as the timer Z count source.
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(4)Programmable wait one-shot generation mode * Mode select Timer mode is selected by setting timer Z operation mode bits (b5,b4) of TYZM to "11". When this mode is selected, set timer Z write control bit (b6) of TYZM to "1" ("writing to only latch" selected). * Count source select The count source is f(XIN)/2, f(XIN)/16 or timer Y underflow. * Interrupt When an underflow occurs, timer Z interrupt request bit (b1) of IREQ is set to "1". * Operation description After reset release, timer Z is operating because the timer Z count stop bit (b7) of TYZM is "0". MCU operates in the programmable wait one-shot generation mode when timer Z operation mode bits (b5, b4) of TYZM is set to "11" after timer Z operation is stopped by setting b7 of TYZM to "1". Timer Z is enabled to accept the one-shot start trigger when "0" is written to b7 of TYZM after the timer count values are set to the timer Z primary latch (TZP) and the timer Z secondary latch (TZS). In this state, when "1" is written to the timer Z one-shot start bit (b0) of ONS, timer Z starts count operation. Unlike the programmable one-shot generation mode, the output of TZOUT pin is not changed until the timer counts TZP and an underflow occurs. When the timer Z counts TZP and an underflow occurs, TZS is reloaded to timer, at the same time, the output of the TZOUT pin is inverted. Timer Z counts down the value of TZP and stops after the output of TZOUT pin is inverted to the same level as the initial state when an underflow occurs. In this time, the next one-shot pulse can be output by writing b0 of ONS to "1" because this bit is initialized to "0". The active edge of the output waveform from TZOUT pin is set by the timer Z output level latch (b5) of PUM. When "0" is set to b5 of PUM, the initial level of timer at stop and the TZP count interval are "L" and inverted to "H" at the same time when an underflow occurs. "H" is output in the count interval of TZS, and the output is inverted to "L" and stopped when an underflow occurs. Also, when "1" is set to b5 of PUM, the initial level of timer at stop and the TZP count interval are "H" and inverted to "L" at the same time when an underflow occurs. "L" is output in the count interval of TZS, and the output is inverted to "H" and stopped when an underflow occurs. When the INT0 pin one-shot trigger control bit (b6) of PUM is set to "1", the one-shot pulse can be output by using the input of INT0 pin as a trigger. The active edge of the pulse input to INT0 pin as the trigger can be selected by the INT0 pin one-shot trigger active edge selection bit (b7) of PUM. The trigger is accepted and the one-shot pulse is generated by the falling edge of INT0 pin input when "0" is set to b7 of PUM or the rising edge of INT0 pin input when "1" is set to the b7 of PUM.
Also, the INT0 interrupt occurs when the trigger is input from the INT0 pin by setting the INT0 interrupt edge selection bit (b0) of the interrupt edge selection register (INTEDGE) and the INT0 interrupt enable bit (b2) of the interrupt control register 1 (ICON1). Even when the trigger by the INT0 pin input is selected, the one-shot pulse can be output by writing to b0 of ONS. Also, in this mode, the waveform output interval of the one-shot pulse can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (b2) to "1". As a result, the waveforms of more accurate resolution can be output. When using the programmable wait one-shot generation mode, note the following; Notes on using the programmable wait one-shot generation mode * When setting and changing TZP, TZS, EXPZP and EXPZS, write to TZP at last because the setting to them is executed all at once by writing to TZP. Even when TZP is not changed, write the same value. The value is reloaded to timer at the beginning of the next primary interval. * Set by software in order not to execute the writing to timer Z primary and the timing of timer underflow simultaneously. When reading the timer Z secondary, the undefined value is read out. However, while timer counts the setting value of the timer Z secondary, the count values at the secondary interval can be identified by reading the timer Z primary. * In this mode, set port P02 which is also used as TZOUT pin to output. * B2 of PUM can be used only when "0016" is set to prescaler Z and f(XIN)/2 or f(XIN)/16 is selected as the timer Z count source.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Timer Y, Z mode register (TYZM : address 002016) Timer Y operation mode bit 0 : Timer mode 1 : Programmable waveform generation mode Not used (return "0" when read) Timer Y write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Y count stop bit 0 : Count start 1 : Count stop Timer Z count source selection bits b5 b4 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Timer Z write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Z count stop bit 0 : Count start 1 : Count stop
Fig. 22 Structure of timer Y, Z mode register
b7 b0
Timer Y, Z waveform output control register (PUM : address 002416) Timer Y primary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Y secondary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Z primary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Z secondary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Y output level latch 0 : "L" output 1 : "H" output Timer Z output level latch 0 : "L" output 1 : "H" output INT0 pin one-shot trigger control bit 0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid INT0 pin one-shot trigger active edge selection bit 0 : Falling edge trigger 1 : Rising edge trigger
Fig. 23 Structure of timer YZ waveform output control register
b7
b0
One-shot start register (ONS : address 002A 16) Timer Z one-shot start bit 0 : One-shot stop @ 1 : One-shot start
@@ @ Not used@ (return "0" when read)
Fig. 24 Structure of one-shot start register
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
Prescaler 1 latch (8)
Timer 1 latch (8)
f(XIN)/16
Prescaler 1 (8) Pulse width HL continuously measurement mode Rising edge detected
Timer 1 (8)
Timer 1 interrupt request bit
Period measurement mode Falling edge detected
P00/CNTR1
CNTR1 active edge switch bit
Data bus
Timer A (low-order) latch (8)
Timer A (high-order) latch (8)
Timer A (low-order) (8) f(XIN)/16 Timer A operation mode bit Timer A count stop bit
Timer A (high-order) (8)
Timer A interrupt request bit
Fig. 25 Block diagram of timer 1 and timer A
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
f(XIN)/16 f(XIN)/2 f(XIN)
Timer X count source selection bits
Prescaler X latch (8) Pulse width Timer mode measurement Pulse output mode mode Prescaler X (8)
Timer X latch (8)
Timer X (8)
P14/CNTR0
CNTR0 active edge switch bit "0" "1"
Timer X interrupt request bit
Event counter mode
Timer X count stop bit CNTR0 interrupt request bit Q Q
CNTR0 active "1" edge switch bit
Toggle flip-flop T R Writing to timer X latch Pulse output mode
Port P14 direction register P03/TXOUT
Port P14 latch
"0"
Pulse output mode
Port P03 latch Data bus P03/TXOUT output valid Port P03 direction register Prescaler Y latch (8) Timer Y count source selection bits f(XIN)/16 f(XIN)/2 Ring oscillator clock RING (ring oscillator output in Fig. 47, 48) Timer Y count stop bit Timer Y primary waveform extension control bit Q P01/TYOUT Port P01 latch Port P01 direction register Q Timer Y output level latch Timer Y secondary waveform extension control bit Prescaler Y (8) Timer Y (8) Timer Y interrupt request bit Timer Y primary latch (8) Timer Y secondary latch (8)
Toggle flip-flop T
Waveform extension function
Programmable waveform gengeration mode
Data bus
Prescaler Z latch (8) Timer Z count source selection bits f(XIN)/16 f(XIN)/2 Prescaler Z (8)
Timer Z primary latch (8)
Timer Z secondary latch (8)
Timer Z (8) Programmable one-shot generation mode Programmable wait one-shot generation mode Timer Z one-shot start bit
Timer Z interrupt request bit
Timer Z count stop bit INT0 pin trigger active edge selection bit P37/INT0 One-shot pulse trigger input Q P02/TZOUT Port P02 latch Port P02 direction register Programmable waveform generation mode Programmable one-shot generation mode Q
INT0 interrupt request bit Timer Z primary waveform extenstion control bit Toggle flip flop T Timer Z output level latch
Waveform extension function
Timer Z secondary waveform extenstion control bit
Fig. 26 Block diagram of timer X, timer Y and timer Z
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O qSerial I/O1
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6) to "1". For clock synchronous serial I/O 1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
Data bus Serial I/O1 control register Address 001A16
Address 001816 Receive buffer register P10/RXD1 Receive shift register Shift clock P12/SCLK1
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
XIN
BRG count source selection bit 1/4
Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4
P13/SRDY1
F/F
Falling-edge detector Shift clock
Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
P11/TXD1
Transmit shift register Transmit buffer register Address 001816 Data bus
Fig. 27 Block diagram of clock synchronous serial I/O1
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 28 Operation of clock synchronous serial I/O1 function
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Data bus Address 001816
Receive buffer register OE Character length selection bit
Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16
P10/RXD1
ST detector
7 bits 8 bits
Receive shift register PE FE SP detector Clock control circuit UART control register Address 001B16
Serial I/O1 synchronous clock selection bit P12/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P11/TXD1 Character length selection bit Transmit buffer register Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI)
XIN
Fig. 29 Block diagram of UART serial I/O1
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit or receive clock
Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1V
Serial output TXD
ST
D0
D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
SP
ST
D0
D1
V
SP Generated at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=0 RBF=1 RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 30 Operation of UART serial I/O1 function [Transmit buffer register/receive buffer register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O1 status register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O1 control register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART control register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TXD1, P12/SCLK1 pin. [Baud rate generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 status register (SIO1STS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O1 control register (SIO1CON : address 001A 16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P13 pin operates as ordinary I/O pin 1: P13 pin operates as S RDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P10 to P13 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P10 to P13operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P11/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read)
Fig. 31 Structure of serial I/O1-related registers
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
qSerial I/O2
The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Note: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected as the synchronized clock. [Serial I/O2 control register] SIO2CON The serial I/O2 control register contains 8 bits which control various serial I/O functions. * Set "0" to bit 3 to receive. * At reception, clear bit 7 to "0" by writing a dummy data to the serial I/O2 register after completion of shift.
b7 b0
Serial I/O2 control register (SIO2CON: address 003016) Internal synchronous clock selection bits 000 : f(XIN)/8 001 : f(XIN)/16 010 : f(XIN)/32 011 : f(XIN)/64 110 : f(XIN)/128 111 : f(XIN)/256 SDATA2 pin selection bit (Note) 0 : I/O port / SDATA2 input 1 : SDATA2 output Not used (returns "0" when read)
Transfer direction selection bit 0 : LSB first 1 : MSB first SCLK2 pin selection bit 0 : External clock (SCLK2 is an input) 1 : Internal clock (SCLK2 is an output) Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed Note : When using it as a SDATA input, set the port P13 direction register to "0".
Fig. 32 Structure of serial I/O2 control registers
Data bus
1/8 1/16 Divider 1/32 1/64 1/128 1/256
XIN
SCLK2 pin
selection bit
"1" "0"
Internal synchronous clock selection bits
SCLK
SCLK2 pin selection bit
"0"
P12/SCLK2
"1"
P12 latch Serial I/O counter 2 (3) Serial I/O2 interrupt request
SDATA2 pin selection bit
"0"
P13/SDATA2
"1"
P13 latch
SDATA2 pin selection bit Serial I/O shift register 2 (8)
Fig. 33 Block diagram of serial I/O2
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2 operation By writing to the serial I/O2 register (address 003116) the serial I/O2 counter is set to "7". After writing, the SDATA2 pin outputs data every time the transfer clock shifts from "H" to "L". And, as the transfer clock shifts from "L" to "H", the SDATA2 pin reads data, and at the same time the contents of the serial I/O2 register are shifted by 1 bit. When the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. * Serial I/O2 counter is cleared to "0". * Transfer clock stops at an "H" level. * Interrupt request bit is set. * Shift completion flag is set. Also, the SDATA2 pin is in a high impedance state after the data transfer is completed. When the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. Notice that the SDATA2 pin is not in a high impedance state on the completion of data transfer. Also, after the receive operation is completed, the transmit/receive shift completion flag is cleared by reading the serial I/O2 register. At transmit, the transmit/receive shift completion flag is cleared and the transmit operation is started by writing to serial I/O2 register.
Synchronous clock
Transfer clock
Serial I/O2 register write signal (Note) SDATA2 at serial I/O2 output transmit SDATA2 at serial I/O2 input receive D0 D1 D2 D3 D4 D5 D6 D7
Serial I/O2 interrupt request bit set Transmit/receive shift completion flag set Note : When the internal clock is selected as the transfer, the S DATA2 pin is in a high impedance state after the data transfer is completed.
Fig. 34 Serial I/O2 timing (LSB first)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
The functional blocks of the A-D converter are described below. [A-D conversion register] AD The A-D conversion register is a read-only register that stores the result of A-D conversion. Do not read out this register during an A-D conversion. [A-D control register] ADCON The A-D control register controls the A-D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at "0" during A-D conversion, and changes to "1" at completion of A-D conversion. A-D conversion is started by setting this bit to "0". [Comparison voltage generator] The comparison voltage generator divides the voltage between AVSS and VREF by 1024, and outputs the divided voltages. [Channel selector] The channel selector selects one of ports P27/AN7 to P20/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A-D conversion register. When A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Because the comparator is constructed linked to a capacitor, set f(XIN) to 500 kHz or more during A-D conversion.
b7
b0
A-D control register (ADCON : address 003416) Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 (Note) 111 : P27/AN7 (Note) Not used (returns "0" when read) AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns "0" when read) Note: These can be used only for 36 pin version.
Fig. 35 Structure of A-D control register
Read 8-bit (Read only address 003516) b7 (Address 003516) b9 b8 b7 b6 b5 b4 b3
b0 b2
Read 10-bit (read in order address 003616, 003516) b7 (Address 003616) b7 (Address 003516) b7 b6 b5 b4 b3 b2 b1 b9
b0 b8 b0 b0
Note: High-order 6-bit of address 003616 returns "0" when read.
Fig. 36 Structure of A-D conversion register
Data bus
b7 A-D control register (Address 0034 16) 3 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 A-D control circuit
b0
A-D interrupt request
Channel selector
A-D conversion register (high-order)
Comparator
(Address 0036 16) (Address 0035 16)
A-D conversion register (low-order) 10 Resistor ladder
VREF
Fig. 37 Block diagram of A-D converter
VSS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register (address 003916) is not set after reset. Writing an optional value to the watchdog timer control register (address 003916) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 003916) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit are read. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (address 003916), the watchdog timer H is set to "FF16" and the watchdog timer L is set to "FF16".
Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is "0", the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz. When this bit is "1", the count source becomes f(XIN)/16. In this case, the detection time is 512 s at f(XIN)=8 MHz. This bit is cleared to "0" after reset. Operation of STP instruction disable bit When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (address 003916). When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed. Once this bit is set to "1", it cannot be changed to "0" by program. This bit is cleared to "0" after reset.
Data bus Write "FF16" to the watchdog timer control register Watchdog timer L (8) 1/16 Write "FF16" to the watchdog timer control register
"0" "1" Watchdog timer H (8)
XIN
Watchdog timer H count source selection bit STP Instruction disable bit STP Instruction Reset circuit Internal reset
RESET
Fig. 38 Block diagram of watchdog timer
b7
b0
Watchdog timer control register (WDTCON: address 003916) Watchdog timer H (read only for high-order 6-bit) STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16
Fig. 39 Structure of watchdog timer control register
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset Circuit
______
The microcomputer is put into a reset status by holding the RESET pin at the "L" level for 2 s or more when the power source voltage is 2.2 to 5.5 V and XIN is in stable oscillation. ______ After that, this reset status is released by returning the RESET pin to the "H" level. The program starts from the address having the contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address. In the case of f() 4 MHz, the reset input voltage must be 0.8 V or less when the power source voltage passes 4.0 V. In the case of f() 2 MHz, the reset input voltage must be 0.48 V or less when the power source voltage passes 2.4 V. In the case of f() 1 MHz, the reset input voltage must be 0.44 V or less when the power source voltage passes 2.2 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2 VCC
Note : Reset release voltage Vcc = 2.2 V
RESET
VCC Power source voltage detection circuit
Fig. 40 Example of reset circuit
Clock from built-in ring oscillator RING f RESET RESETOUT SYNC Address Data
? ? ? ? ? ? ? ? ? ? FFFC ADL FFFD
ADH,ADL
ADH
Reset address from the vector table
8-13 clock cycles
Notes 1 : A built-in ring oscillator applies about RING*2 MHz, f*250 kHz frequency clock at average of Vcc = 5 V. 2 : The mark "?" means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET.
Fig. 41 Timing diagram at reset
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Pull-up control register (6) Port P1P3 control register (7) Serial I/O1 status register (8) Serial I/O1 control register (9) UART control register (10) Timer A mode register (11) Timer A (low-order) (12) Timer A (high-order) (13) Timer Y, Z mode register (14) Prescaler Y (15) Timer Y secondary (16) Timer Y primary (17) Timer Y, Z waveform output control register (18) Prescaler Z (19) Timer Z secondary (20) Timer Z primary (21) Prescaler 1 (22) Timer 1 (23) One-shot start register (24) Timer X mode register (25) Prescaler X (26) Timer X (27) Timer count source set register (28) Serial I/O2 control register (29) Serial I/O2 register (30) A-D control register (31) MISRG (32) Watchdog timer control register (33) Interrupt edge selection register (34) CPU mode register (35) Interrupt request register 1 (36) Interrupt request register 2 (37) Interrupt control register 1 (38) Interrupt control register 2 (39) Processor status register (40) Program counter 000116 000316 000516 000716 001616 001716 001916 001A16 001B16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 003016 003116 003416 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL)
X 1 0 1 1 X
Register contents
0016 X X 0 0 0 0 0
0016 0016 0016 0016 0 0 0 0 0 0 1
0216 1 1 0 0 0 0 0
0016 FF16 FF16 0016 FF16 FF16 FF16 0016 FF16 FF16 FF16 FF16 0116 0016 0016 FF16 FF16 0016 0016 0016 1016 0016 0 1 1 1 1 1 1
0016 0 0 0 0 0 0 0
0016 0016 0016 0016 X X X X 1 X X
Contents of address FFFD16 Contents of address FFFC16
Note X : Undefined
Fig. 42 Internal status of microcomputer at reset
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. Set the constants of the resistor and capacitor when an RC oscillator is used, so that a frequency variation due to LSI variation and resistor and capacitor variations may not exceed the standard input frequency.
qSwitch of ceramic and RC oscillations
After releasing reset the operation starts by starting a built-in ring oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register.
qDouble-speed mode
When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected.
qCPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU "M37540RSS" is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
qOscillation control
* Stop mode When the STP instruction is executed, the internal clock f stops at an "H" level and the XIN oscillator stops. At this time, timer 1 is set to "0116" and prescaler 1 is set to "FF16" when the oscillation stabilization time set bit after release of the STP instruction is "0". On the other hand, timer 1 and prescaler 1 are not set when the above bit is "1". Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 1. When an external interrupt is accepted, oscillation is restarted but the internal clock f remains at "H" until timer 1 underflows. As soon as timer 1 underflows, the internal clock f is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an "L" level to the RESET pin while oscillation becomes stable. Also, the STP instruction cannot be used while CPU is operating by a ring oscillator. * Wait mode If the WIT instruction is executed, the internal clock f stops at an "H" level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. When the STP status is released, prescaler 1 and timer 1 will start counting clock which is XIN divided by 16, so set the timer 1 interrupt enable bit to "0" before the STP instruction is executed. Note For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used.
qClock division ratio, XIN oscillation control, ring oscillator control
The state transition shown in Fig. 49 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), ring oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 49.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
MISRG(address 003816) Oscillation stabilization time set bit after release of the STP instruction 0: Set "0116" in timer1, and "FF16" in prescaler 1 automatically 1: Not set automatically Reserved bits (return "0" when read) (Do not write "1" to these bits) Not used (return "0" when read)
XIN
XOUT
CIN
COUT
Fig. 46 Structure of MISRG
Fig. 43 External circuit of ceramic resonator
XIN
XOUT R C
Fig. 44 External circuit of RC oscillation
XIN
XOUT Open
External oscillation circuit VCC VSS
Fig. 45 External clock input circuit
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN Rf
XOUT Rd
1/2
1/4
1/2
Prescaler 1
Timer 1
Main clock division ratio selection bit Middle-speed mode High-speed mode Double-speed mode Ring oscillator (Note)
Timing (Internal clock)
1/8
Ring oscillator mode
QS R STP instruction WIT instruction
S R
Q
Q
S R STP instruction
Reset Interrupt disable flag l Interrupt request
Note: Ring oscillator is used only for starting.
Fig. 47 Block diagram of internal clock generating circuit (for ceramic resonator)
XOUT
XIN
1/2
1/4
1/2
Prescaler 1
Timer 1
Delay Main clock division ratio selection bit Middle-speed mode High-speed mode Double-speed mode Ring oscillator (Note)
Timing (Internal clock)
1/8
Ring oscillator mode
QS R STP instruction WIT instruction
S R
Q
Q
S R STP instruction
Reset Interrupt disable flag l Interrupt request
Fig. 48 Block diagram of internal clock generating circuit (for RC oscillation)
Note: Ring oscillator is used only for starting.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CM412
State 1 Operation clock source: X IN XIN oscillation enabled Ring oscillator stop CM302 CM7,6102 CM302
CM7,610 2 CM41 2 CM30 2
CM312 State 2 CM7,6NOT(102) CM402 CM312 CM7,6102 CM412 CM7,6NOT(102) Operation clock source: X IN XIN oscillation enabled Ring oscillator enalbed CM7,6102 CM412
CM7,6NOT(102) CM312
State 3 (initial state after reset) Operation clock source: Ring oscillator XIN oscillation enabled Ring oscillator enalbed
CM312
CM412 CM7,6NOT(102) CM402 CM402 State 4 (low power dissipation mode by ring oscillator) Operation clock source: Ring oscillator CM312
Notes on switch of clock (1) Execute the state transition from state 3 to state 2 after stabilizing XIN oscillation. (2) Do not execute the state transition shown . (3) In operation clock source = XIN, the double-speed mode, high-speed mode, and middle-speed mode can be selected for the CPU clock division ratio. (4) In operation clock source = ring oscillator, the middle-speed mode is selected for the CPU clock division ratio. (5) Do not stop the clock selected as the operation clock because of setting of CM3, 4.
XIN oscillation stop Ring oscillator enalbed
Fig. 49 State transition
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is "1". After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500kHz or more during A-D conversion. Do not execute the STP instruction during A-D conversion.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode.
Interrupts
The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction.
CPU Mode Register
The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected.
Decimal Calculations
* For calculations in decimal notation, set the decimal mode flag D to "1", then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. * In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid.
State transition
Do not stop the clock selected as the operation clock because of setting of CM3, 4.
Timers
* When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X.
NOTES ON USE Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended.
Ports
* The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. * P26/AN6, P27/AN7, P35 (LED5), P36/INT1 pins do not exist in the 32-pin version. Stabilize the internal level by setting the port direction registers of these ports to output or setting P35, P36 pull-up control bits of the pull-up control register (PULL) to ON by program.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 5 Special programming adapter Package Name of Programming Adapter 32P4B 32P6B-A 36P2R-A PCA7435SPG02 PCA7435GPG02 PCA7435FPG02
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 50 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150 C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 50 Programming and testing of One Time PROM version
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS 1.7540Group (General purpose)
Applied to: M37540M4-XXXFP/SP/GP, M37540E8FP/SP/GP
Absolute Maximum Ratings (General purpose)
Table 6 Absolute maximum ratings Parameter Symbol VCC VI VI VI VO Pd Topr Tstg Power source voltage Input voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature P00-P07, P10-P14, P20-P27, P30-P37, VREF RESET, XIN CNVSS (Note 1) P00-P07, P10-P14, P20-P27, P30-P37, XOUT Ta = 25C All voltages are based on VSS. Output transistors are cut off. Unit V V V V V mW C C
Conditions
Ratings -0.3 to 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to 13 -0.3 to VCC + 0.3 300 (Note 2) -20 to 85 -40 to 125
Note 1: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version. 2: 200 mW for the 32P6B package product.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Recommended Operating Conditions (General purpose)
Table 7 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol Parameter Min. Typ. VCC Power source voltage (ceramic) f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 1 MHz (Double-speed mode) Power source voltage (RC) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 1 MHz (High-, Middle-speed mode) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage "H" input voltage (TTL input level selected) "H" input voltage "L" input voltage "L" input voltage (TTL input level selected) "L" input voltage "L" input voltage "H" total peak output current (Note 2) "L" total peak output current (Note 2) "L" total peak output current (Note 2) "H" total average output current (Note 2) "L" total average output current (Note 2) "L" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 P10, P12, P13, P36, P37 (Note 1) RESET, XIN P00-P07, P10-P14, P20-P27, P30-P37 P10, P12, P13, P36, P37 (Note 1) RESET, CNVSS XIN P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 2.0 0.8VCC 2.0 0.8VCC 0 0 0 0 4.0 2.4 2.2 4.0 2.4 2.2 4.0 2.4 2.2 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 VCC VCC VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC -80 80 60 -40 40 30
Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Unit V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA
Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Recommended Operating Conditions (General purpose)(continued)
Table 8 Recommended operating conditions (2) (VCC = 2.2 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol Parameter Min. Typ. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) "H" peak output current (Note 1) "L" peak output current (Note 1) "L" peak output current (Note 1) "H" average output current (Note 2) "L" average output current (Note 2) "L" average output current (Note 2) Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at RC oscillation Internal clock oscillation frequency (Note 3) at RC oscillation Internal clock oscillation frequency (Note 3) at RC oscillation P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 VCC = 4.0 to 5.5 V Double-speed mode VCC = 2.4 to 5.5 V Double-speed mode VCC = 2.2 to 5.5 V Double-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 2.2 to 5.5 V High-, Middle-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 2.2 to 5.5 V High-, Middle-speed mode
Max. -10 10 30 -5 5 15 4 2 1 8 4 2 4 2 1
Unit mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz MHz MHz
Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Electrical Characteristics (General purpose)
Table 9 Electrical characteristics (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.2 to 5.5 V VOL "L" output voltage P00-P07, P10-P14, P20-P27, P37 IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.2 to 5.5 V VOL "L" output voltage P30-P36 IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.2 to 5.5 V VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis Hysteresis Hysteresis "H" input current CNTR0, CNTR1, INT0, INT1(Note 2) P00-P07 (Note 3) RXD, SCLK1, SCLK2, SDATA2 (Note 2) RESET P00-P07, P10-P14, P20-P27, P30-P37 RESET XIN P00-P07, P10-P14, P20-P27, P30-P37 RESET, CNVSS XIN P00-P07, P30-P37 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors "off" Double-speed mode, f(XIN) = 4 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state) Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8 MHz, VCC = 5 V Ta = 25 C All oscillation stopped (in STP state) Output transistors "off" Ta = 85 C 2.0 5.0 TBD 5.0 2.0 1.6 TBD 0.7 0.1 1.0 10 -4.0 -0.2 -0.5 5.5 TBD TBD TBD TBD 4.0 -5.0 0.4 0.5 0.5 5.0 Limits Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 Typ. Max. Unit V V V V V V V V V V V A
IIH IIH IIL
"H" input current "H" input current "L" input current
5.0
A A A
IIL IIL IIL VRAM ICC
"L" input current "L" input current "L" input current RAM hold voltage
-5.0
A A mA V mA mA mA mA mA mA mA A A
Power source current
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter Characteristics (General purpose)
Table 10 A-D Converter characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol -- -- -- VOT VFST Resolution Linearity error Differential nonlinear error Zero transition voltage VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V Full scale transition voltage VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV RLADDER IVREF Conversion time Ladder resistor Reference power source input current VREF = 5.0 V VREF = 3.0 V II(AD) A-D port input current 50 30 35 150 90 200 120 5.0 A 0 0 5105 3060 5 3 5115 3069 Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 20 15 5125 3075 122 Unit Bits LSB LSB mV mV mV mV tc(XIN) k A
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing Requirements (General purpose)
Table 11 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(RxD1-SCLK1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Parameter Limits Min. 2 125 50 50 200 80 80 200 80 80 2000 950 950 400 200 1000 400 400 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ns Serial I/O2 input hold time th(SCLK2-SDATA2) 200 Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
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MITSUBISHI MICROCOMPUTERS
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 12 Timing requirements (2) (VCC = 2.2 to 5.5 V or 2.4 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(SDATA1-SCLK1) th(SCLK1-SDATA1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time Serial I/O1 clock input "H" pulse width Serial I/O1 clock input "L" pulse width Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V Parameter Limits Min. 2 500 250 200 100 200 100 1000 500 460 230 460 230 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 4000 2000 1900 950 1900 950 400 400 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Switching Characteristics (General purpose)
Table 13 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 10 10 0 30 30 30 30 tC(SCLK2)/2-30 tC(SCLK2)/2-30 140 -30 30 30 Limits Min. tC(SCLK1)/2-30 tC(SCLK1)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded. Table 14 Switching characteristics (2) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 20 20 0 50 50 50 50 tC(SCLK2)/2-50 tC(SCLK2)/2-50 350 TBD TBD TBD Limits Min. TBD TBD TBD Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded.
Measured output pin 100 pF
/// CMOS output Switching characteristics measurement circuit diagram (General purpose)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR0) tWH(CNTR0) tWL(CNTR0) 0.2VCC
CNTR0
0.8VCC
tC(CNTR1) tWH(CNTR1) tWL(CNTR1) 0.2VCC
CNTR1
0.8VCC
tWH(CNTR0)
tWL(CNTR0) 0.2VCC
INT0, INT1
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
tf
tWL(SCLK1) 0.2VCC
tC(SCLK1) tr 0.8VCC
tWH(SCLK1)
SCLK1
tsu(SDATA1-SCLK1)
th(SCLK1-SDATA1)
RXD1 (at receive)
td(SCLK1-SDATA1)
0.8VCC 0.2VCC tv(SCLK1-SDATA1)
TXD1 (at transmit)
tf
tWL(SCLK2) 0.2VCC
tC(SCLK2) tr 0.8VCC
tWH(SCLK2)
SCLK2
tsu(SDATA2-SCLK2)
th(SCLK2-SDATA2)
SDATA2 (at receive)
td(SCLK2-SDATA2)
0.8VCC 0.2VCC tv(SCLK2-SDATA2)
SDATA2 (at transmit)
Fig. 51 Timing chart (General purpose)
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS 2.7540Group (Extended operating temperature version)
Applied to: M37540M4T-XXXFP/GP
Absolute Maximum Ratings (Extended operating temperature version)
Table 15 Absolute maximum ratings Parameter Symbol VCC VI VI VO Pd Topr Tstg Power source voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature P00-P07, P10-P14, P20-P27, P30-P37, VREF RESET, XIN, CNVSS P00-P07, P10-P14, P20-P27, P30-P37, XOUT Ta = 25C All voltages are based on VSS. Output transistors are cut off. Unit V V V V mW C C
Conditions
Ratings -0.3 to 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 300 (Note) -40 to 85 -65 to 150
Storage temperature Note : 200 mW for the 32P6B package product.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Recommended Operating Conditions (Extended operating temperature version)
Table 16 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Min. Typ. VCC Power source voltage (ceramic) f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) Power source voltage (RC) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage "H" input voltage (TTL input level selected) "H" input voltage "L" input voltage "L" input voltage (TTL input level selected) "L" input voltage "L" input voltage "H" total peak output current (Note 2) "L" total peak output current (Note 2) "L" total peak output current (Note 2) "H" total average output current (Note 2) "L" total average output current (Note 2) "L" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 P10, P12, P13, P36, P37 (Note 1) RESET, XIN P00-P07, P10-P14, P20-P27, P30-P37 P10, P12, P13, P36, P37 (Note 1) RESET, CNVSS XIN P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 2.0 0.8VCC 2.0 0.8VCC 0 0 0 0 f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) 4.0 2.4 2.2 4.0 2.4 4.0 2.4 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 VCC VCC VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC -80 80 60 -40 40 30
Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Unit V V V V V V V V V V V V V V V V mA mA mA mA mA mA
Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Recommended Operating Conditions (Extended operating temperature version)
Table 17 Recommended operating conditions (2) (VCC = 2.2 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Min. Typ. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) "H" peak output current (Note 1) "L" peak output current (Note 1) "L" peak output current (Note 1) "H" average output current (Note 2) "L" average output current (Note 2) "L" average output current (Note 2) Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at RC oscillation Internal clock oscillation frequency (Note 3) at RC oscillation P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P10-P14, P20-P27, P37 P30-P36 VCC = 4.0 to 5.5 V Double-speed mode VCC = 2.4 to 5.5 V Double-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 2.2 to 5.5 V High-, Middle-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode
Max. -10 10 30 -5 5 15 4 2 8 4 2 4 2
Unit mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz
Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Extended operating temperature version)
Table 18 Electrical characteristics (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.2 to 5.5 V VOL "L" output voltage P00-P07, P10-P14, P20-P27, P37 IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.2 to 5.5 V VOL "L" output voltage P30-P36 IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.2 to 5.5 V VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis Hysteresis Hysteresis "H" input current CNTR0, CNTR1, INT0, INT1(Note 2) P00-P07 (Note 3) RXD1, SCLK1, SCLK2, SDATA2 (Note 2) RESET P00-P07, P10-P14, P20-P27, P30-P37 RESET XIN P00-P07, P10-P14, P20-P27, P30-P37 RESET, CNVSS XIN P00-P07, P30-P37 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors "off" Double-speed mode, f(XIN) = 4 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state) Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8 MHz, VCC = 5 V Ta = 25 C All oscillation stopped (in STP state) Output transistors "off" Ta = 85 C 2.0 5.0 TBD 5.0 2.0 1.6 TBD 0.7 0.1 1.0 10 -4.0 -0.2 -0.5 5.5 TBD TBD TBD TBD 4.0 -5.0 0.4 0.5 0.5 5.0 Limits Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 Typ. Max. Unit V V V V V V V V V V V A
IIH IIH IIL
"H" input current "H" input current "L" input current
5.0
A A A
IIL IIL IIL VRAM ICC
"L" input current "L" input current "L" input current RAM hold voltage
-5.0
A A mA V mA mA mA mA mA mA mA A A
Power source current
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter Characteristics (Extended operating temperature version)
Table 19 A-D Converter characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol -- -- -- VOT VFST Resolution Linearity error Differential nonlinear error Zero transition voltage VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V Full scale transition voltage VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV RLADDER IVREF Conversion time Ladder resistor Reference power source input current VREF = 5.0 V VREF = 3.0 V II(AD) A-D port input current 50 30 35 150 90 200 120 5.0 A 0 0 5105 3060 5 3 5115 3069 Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 20 15 5125 3075 122 Unit Bits LSB LSB mV mV mV mV tc(XIN) k A
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing Requirements (Extended operating temperature version)
Table 20 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(RxD1-SCLK1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Parameter Limits Min. 2 125 50 50 200 80 80 200 80 80 2000 950 950 400 200 1000 400 400 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ns Serial I/O2 input hold time th(SCLK2-SDATA2) 200 Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
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Table 21 Timing requirements (2) (VCC = 2.2 to 5.5 V or 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(SDATA1-SCLK1) th(SCLK1-SDATA1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time Serial I/O1 clock input "H" pulse width Serial I/O1 clock input "L" pulse width Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V VCC = 2.2 to 5.5 V VCC = 2.4 to 5.5 V Parameter Limits Min. 2 500 250 200 100 200 100 1000 500 460 230 460 230 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 4000 2000 1900 950 1900 950 400 400 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Switching Characteristics (Extended operating temperature version)
Table 22 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 10 10 0 30 30 30 30 tC(SCLK2)/2-30 tC(SCLK2)/2-30 140 -30 30 30 Limits Min. tC(SCLK1)/2-30 tC(SCLK1)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded. Table 23 Switching characteristics (2) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 20 20 0 50 50 50 50 tC(SCLK2)/2-50 tC(SCLK2)/2-50 350 TBD TBD TBD Limits Min. TBD TBD TBD Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Pin XOUT is excluded.
Measured output pin 100 pF
/// CMOS output Switching characteristics measurement circuit diagram (General purpose)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR0) tWH(CNTR0) tWL(CNTR0) 0.2VCC
CNTR0
0.8VCC
tC(CNTR1) tWH(CNTR1) tWL(CNTR1) 0.2VCC
CNTR1
0.8VCC
tWH(CNTR0)
tWL(CNTR0) 0.2VCC
INT0, INT1
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
tf
tWL(SCLK1) 0.2VCC
tC(SCLK1) tr 0.8VCC
tWH(SCLK1)
SCLK1
tsu(SDATA1-SCLK1)
th(SCLK1-SDATA1)
RXD1 (at receive)
td(SCLK1-SDATA1)
0.8VCC 0.2VCC tv(SCLK1-SDATA1)
TXD1 (at transmit)
tf
tWL(SCLK2) 0.2VCC
tC(SCLK2) tr 0.8VCC
tWH(SCLK2)
SCLK2
tsu(SDATA2-SCLK2)
th(SCLK2-SDATA2)
SDATA2 (at receive)
td(SCLK2-SDATA2)
0.8VCC 0.2VCC tv(SCLK2-SDATA2)
SDATA2 (at transmit)
Fig. 52 Timing chart (Extended operating temperature version)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
36P2R-A
EIAJ Package Code SSOP36-P-450-0.80
36
Plastic 36pin 450mil SSOP
JEDEC Code - Weight(g) 0.53
19
Lead Material Alloy 42
e
b2
HE
E
e1
F
Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 - - - - 0.05 - 2.0 - 0.5 0.4 0.35 0.2 0.15 0.13 15.2 15.0 14.8 8.6 8.4 8.2 - 0.8 - 12.23 11.93 11.63 0.7 0.5 0.3 - 1.765 - - 0.7 - - - 0.85 0.15 - - 0 - 10 - 0.5 - - 11.43 - - 1.27 -
Symbol
1 18
A
G
D A2 e y
b
A1
A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2
L1
z Z1 Detail G Detail F
32P6B-A
EIAJ Package Code LQFP32-P-77-0.80 JEDEC Code - Weight(g) 0.17 Lead Material Alloy 42
L
c
Plastic 32pin 7!7mm body LQFP
MD e
HD D
32 25
b2
I2 Recommended Mount Pad
24
1
Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3 A3
8
17
9
16
A e L1 F A2
x y b2 I2 MD ME
A1
b
x
M
Detail F
Lp
c
y
L
Dimension in Millimeters Min Nom Max 1.7 - - 0.1 0.2 0 1.4 - - 0.3 0.35 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.2 0.1 - - 0 10 - 0.5 - - - - 1.0 7.4 - - - - 7.4
E HE
ME
I2
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7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
32P4B
EIAJ Package Code SDIP32-P-400-1.78 JEDEC Code - Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy
Plastic 32pin 400mil SDIP
32
17
1
16
D Symbol A A1 A2 b b1 b2 c D E e e1 L
e SEATING PLANE
b1
b
b2
Dimension in Millimeters Min Nom Max - - 5.08 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 - 1.778 - - 10.16 - 3.0 - - 0 - 15
A
62
L
A1
A2
e1
E
c
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
*
(c) 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Nov. 1999. Specifications subject to change without notice.
REVISION HISTORY
Rev. No. 1.0 First Edition Revision Description
7540 Group DATA SHEET
Rev. date 991122
(1/1)

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